The present invention generally relates to semiconductor processing and, more particularly, the present invention relates to a system and method for determining surface properties of a feature on a substrate.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers (e.g., at submicron levels). In order to accomplish such high device packing density, smaller and smaller features sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, etc.) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The transfer of patterns to the photoresist layer involves the use of optical aligners. Optical aligners are machines that contain a variety of subsystems that work together to form the imaging function. Such optical aligners include: (1) an illumination source which provides the optical energy (UV light in the above example) for transforming the photoresist via exposure, (2) an optical subsystem that focuses the circuit patterns onto the photoresist surface and allows for controlled exposure times, and (3) a movable stage that holds the wafer being exposed.
The goal of a high performance lithography system is to provide a high resolution, repeatable system which reduces the linewidth of features produced thereby. In addition to providing small, repeatable linewidths, it is also desirable to provide linewidth uniformity across the image field. That is, it is desirable to provide a lithography system in which a designer can expect the linewidth of various features across the image field to fall within a predetermined range of a nominal, target value. As lithography systems and processes continue to improve, the average linewidth variation across the image field continues to decrease, thus indicating greater linewidth uniformity.
It is important for lithography developers to ascertain a linewidth variation across the image field in order to properly characterize and develop new lithography components and processes (e.g., exposure processes, mask materials, photoresists, imaging systems, etc.) to further enhance linewidth uniformity. As feature linewidths and the average linewidth variations associated with features continue to shrink, however, distilling the average linewidth variations that are due to the lithography system from the linewidth variations due to other phenomena becomes increasingly difficult. One such phenomenon is called line edge roughness (LER) and refers to the variations on the sidewalls of patterned features.
LER occurs in patterned features and is caused, for example, by a corresponding LER within an overlying photoresist, which is used as a mask for the patterning of the features. LER in photoresist masks is caused by various factors, including LER on the chrome patterns which reside on the reticle (often called mask edge roughness), the image contrast of the system used in generating the photomask. pattern, the plasma etch with which the photoresist pattern is formed, the photoresist material properties and chemistry and the photoresist processing scheme. The LER in the overlying photoresist mask is then transferred into the underlying film (e.g., metal, polysilicon, etc.). In addition to LER in the photoresist mask, the plasma etch used in patterning the underlying film further contributes to the LER of the patterned feature.
As feature sizes continue to shrink, the contribution of LER to the entire feature linewidth variation becomes more pronounced and thus it is important to separate or distill the LER from average linewidth variations caused by the lithography system and process. With such information, each component that makes up the entire linewidth variation (e.g., LER and the lithography system) can be separately characterized and processes can be developed to reduce each component. When a nominal linewidth is substantially large (e.g., a poor quality lithography process having large linewidth variations), a nonuniformity is relatively small with respect thereto and thus may be effectively ignored. In contrast, as the linewidth dimensions become smaller, a similarly dimensioned nonuniformity becomes more pronounced with respect to the entire linewidth variation and, therefore, should be taken into account. More particularly, it is important for the lithography developer to separate LER from average linewidth variations due to the lithography system and process so that subsequent process development can properly focus on each component of linewidth variation separately. In addition, as device features continue to shrink, LER impacts the process control, for example, causing the channel lengths of various transistors to vary from one another beyond a maximum threshold and thus undesirably resulting in device performance variations. The LER is a significant concern in lithography processes employing an exposure wavelength of 193 nm or less.
The present invention relates to a system and related method for determining properties of a patterned feature, which may include line edge roughness (LER) and/or linewidth, wherein the patterned feature is scanned by a scanning system having a plurality of probe tips. Data obtained from the plurality of tips is aggregated and processed to quantify selected characteristics of the patterned feature. The quantified characteristics may then be employed to refine the associated lithography processes to mitigate undesirable LER and/or linewidth variations.
One aspect of the present invention provides a system for determining properties of a feature located at a surface of a substrate. The system includes a scanning system having a plurality of probe tips operable to traverse a surface of the substrate. Each probe tip provides measurement data indicative of topographical features scanned thereby. A control system is operable to aggregate measurement data from the plurality of probe tips to determine feature properties based on the aggregated measurement data.
According to another aspect of the invention, the system for determining properties of a feature is operable to determine a line edge roughness of a developed photoresist feature. The invention further comprises a processor and control system associated with the determination system which takes the line edge roughness data associated with the photoresist feature and provides one or more feedback control signals to an exposure system for performing a post developments blanket exposure of the photoresist feature. More particularly, the system is operable to customize the blanket exposure (e.g., temperature and duration) as a function of the determined line edge roughness. The blanket exposure results in a change in the photoresist chemistry resulting in a xe2x80x9cpull-backxe2x80x9d associated with the edges of the photoresist feature due to surface tension, thereby reducing the line edge roughness associated therewith. The reworked substrate is then available for subsequent processing, as may be desired.
Another aspect of the present invention provides a method for determining properties of a feature located at a surface of a substrate. The method includes employing a plurality of probe tips to scan the surface of the substrate and adjusting the position of the probe tips between consecutive scanning intervals. Measurement data obtained for each probe tip during each scanning interval is stored and the measurement data associated with a feature are aggregated. Feature characteristics are then determined as a function of the aggregated measurement data associated with the feature.
According to another aspect of the present invention, line edge roughness data may be employed to adjust operating characteristics of an associated semiconductor process so as to mitigate line edge roughness.
To the accomplishment of the foregoing and related ends, certain illustrative aspects of the invention are described herein in connection with the following description and the annexed drawings. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such aspects and their equivalents.